1. Field of the Invention
The present invention relates to electronic device testing, and more particularly to integrated circuit (IC) testing using few device pins.
2. Description of the Related Art
Reduced pin count testing of electronic devices has been implemented in various ways. One way is to incorporate built-in self test (BIST) circuits into the device design. During testing, the BIST circuit translates incoming signals on a few pins into tests required to test and diagnose the device under test (DUT) and returns response signals containing test results.
Another way is to employ simultaneous bidirectional signaling (SBS) to combine the input to the DUT and the output from the DUT on a single line. This technique is described in a commonly owned application entitled, “A Very Small Pin Count IC Tester,” Ser. No. 10/376,025, filed Feb. 27, 2003, the entire contents of which are incorporated by reference herein. The use of SBS allows a single line to be used simultaneously for both input and output for the DUT. Hence, the time required for the test as well as the number of pins involved with the test are reduced.
Even with these reductions in the pin count and the resulting increase in the parallelism of the testing and decrease in the overall cost of testing multiple devices on a wafer, testing still remains very expensive.